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8-channel, 16-/14-bit, serial input, voltage output dac ad5362/ad5363 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 8-channel dac in 52-lead lqfp and 56-lead lfcsp packages guaranteed monotonic to 16/14 bits nominal output voltage range of ?10 v to +10 v multiple output voltage spans available thermal shutdown function channel monitoring multiplexer gpio function system calibration function allowing user-programmable offset and gain channel grouping and addressing features data error checking feature spi-compatible serial interface 2.5 v to 5.5 v digital interface digital reset ( reset ) clear function to user-defined siggndx simultaneous update of dac outputs applications instrumentation industrial control systems level setting in automatic test equipment (ate) variable optical attenuators (voa) optical line cards functional block diagram serial interface 8 6 nn 8 8 14 n 14 14 sdi sclk sdo sync busy reset clr state machine control register gpio register gpio mon_out mon_in1 mon_in0 pec temp_out bin/2scomp temp sensor ad5362/ ad5363 n = 16 for ad5362 n = 14 for ad5363 a/b select register to mux 2s dac 4 register ofs0 register offset dac 0 offset dac 1 dac 4 buffer buffer buffer buffer group 0 group 1 output buffer and power- down control output buffer and power- down control output buffer and power- down control output buffer and power- down control vref0 vout0 vout1 vout2 vout4 vout5 vout6 vout7 vout3 siggnd0 siggnd1 vref1 n n n n n n n n x1 register m register c register mux 2 dv cc v dd v ss agnd dgnd ldac 2 mux vout0 to vout7 a/b mux x2a register x2b register nn 8 8 a/b select register to mux 2s dac 0 register dac 0 n n n n n n n x1 register m register c register mux 2 a/b mux x2a register x2b register n n dac 7 register dac 7 n n n n n n n x1 register m register c register mux 2 a/b mux x2a register x2b register n n dac 3 register dac 3 n n n n n n n x1 register m register c register mux 2 a/b mux x2a register x2b register ofs1 register 05762-001 figure 1.
ad5362/ad5363 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 ac characteristics ........................................................................ 6 timing characteristics ................................................................ 7 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 terminology .................................................................................... 15 theory of operation ...................................................................... 16 dac architecture ....................................................................... 16 channel groups .......................................................................... 16 a/b registers and gain/offset adjustment ............................ 17 offset dacs ................................................................................ 17 output amplifier ........................................................................ 18 transfer function ....................................................................... 18 reference selection .................................................................... 18 calibration ................................................................................... 19 additional calibration ............................................................... 19 reset function ............................................................................ 20 clear function ............................................................................ 20 busy and ldac functions...................................................... 20 bin /2scomp pin ...................................................................... 20 temperature sensor ................................................................... 20 monitor function ....................................................................... 21 gpio pin ..................................................................................... 21 power-down mode .................................................................... 21 thermal shutdown function ................................................... 21 toggle mode ................................................................................ 21 serial interface ................................................................................ 22 spi write mode .......................................................................... 22 spi readback mode ................................................................... 22 register update rates ................................................................ 22 packet error checking ............................................................... 23 channel addressing and special modes ................................. 23 special function mode .............................................................. 24 applications information .............................................................. 26 power supply decoupling ......................................................... 26 power supply sequencing ......................................................... 26 interfacing examples ................................................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 28 revision history 3/ 08rev. 0 to rev. a added 56-lead lfcsp_vq .............................................. universal changes to table 2 ............................................................................ 4 added t 23 parameter ......................................................................... 7 changes to figure 4 .......................................................................... 8 changes to table 6 .......................................................................... 11 changes to a/b registers and gain/offset adjustment section .............................................................................................. 17 changes to calibration section .................................................... 19 changes to reset function section and busy and ldac functions section ........................................................................... 20 changes to channel addressing and special modes section .. 23 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 1/08revision 0: initial version
ad5362/ad5363 rev. a | page 3 of 28 general description the ad5362/ad5363 contain eight 16-/14-bit dacs in a single 52-lead lqfp package or 56-lead lfcsp package. the devices provide buffered voltage outputs with a span of 4 the reference voltage. the gain and offset of each dac can be independently trimmed to remove errors. for even greater flexibility, the device is divided into two groups of four dacs, and the output range of each group can be independently adjusted by an offset dac. the ad5362/ad5363 offer guaranteed operation over a wide supply range with v ss from ?16.5 v to ?4.5 v and v dd from 8 v to 16.5 v. the output amplifier headroom requirement is 1.4 v, operating with a load current of 1 ma. the ad5362/ad5363 have a high speed 4-wire serial interface that is compatible with spi, qspi?, microwire?, and dsp interface standards and can handle clock speeds of up to 50 mhz. all the outputs can be updated simultaneously by taking the ldac input low. each channel has a programmable gain and an offset adjust register. each dac output is gained and buffered on chip with respect to an external siggndx input. the dac outputs can also be switched to siggndx via the clr pin. table 1. high channel count bipolar dacs model resolution (bits) nominal output span output channels linearity error (lsb) ad5360 16 4 v ref (20 v) 16 4 ad5361 14 4 v ref (20 v) 16 1 ad5362 16 4 v ref (20 v) 8 4 ad5363 14 4 v ref (20 v) 8 1 ad5370 16 4 v ref (12 v) 40 4 ad5371 14 4 v ref (12 v) 40 1 ad5372 16 4 v ref (12 v) 32 4 ad5373 14 4 v ref (12 v) 32 1 ad5378 14 8.75 v 32 3 ad5379 14 8.75 v 40 3
ad5362/ad5363 rev. a | page 4 of 28 specifications dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?16.5 v to ?4.5 v; v ref = 5 v; agnd = dgnd = siggnd0 = siggnd1 = 0 v; r l = open circuit; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments accuracy resolution 16 bits ad5362 14 bits ad5363 integral nonlinearity (inl) 4 lsb max ad5362 1 lsb max ad5363 differential nonlinearity (dnl) 1 lsb max guaranteed monotonic by design over temperature zero-scale error 15 mv max before calibration full-scale error 20 mv max before calibration gain error 0.1 % fsr before calibration zero-scale error 2 1 lsb typ after calibration full-scale error 2 1 lsb typ after calibration span error of offset dac 75 mv max see the offset dacs section for details voutx 3 temperature coefficient 5 ppm fsr/c typ includes linearity, offset, and gain drift dc crosstalk 2 180 v max typically 20 v; measured channel at midscale, full-scale change on any other channel reference inputs (vref0, vref1) 2 vrefx input current 10 a max per input; typically 30 na vrefx range 2 2/5 v min/v max 2% for specified operation siggnd0 and siggnd1 inputs 2 dc input impedance 50 k min typically 55 k input range 0.5 v min/v max siggndx gain 0.995/1.005 min/max output characteristics 2 output voltage range v ss + 1.4 v min i load = 1 ma v dd ? 1.4 v max i load = 1 ma nominal output voltage range ?10 to +10 v short-circuit current 15 ma max voutx 3 to dv cc , v dd , or v ss load current 1 ma max capacitive load 2200 pf max dc output impedance 0.5 max monitor pin (mon_out) 2 output impedance dac output at positive full scale 1000 typ dac output at negative full scale 500 typ three-state leakage current 100 na typ continuous current limit 2 ma max digital inputs input high voltage 1.7 v min dv cc = 2.5 v to 3.6 v 2.0 v min dv cc = 3.6 v to 5.5 v input low voltage 0.8 v max dv cc = 2.5 v to 5.5 v input current 1 a max reset , sync , sdi, and sclk pins 20 a max clr , bin /2scomp, and gpio pins input capacitance 2 10 pf max
ad5362/ad5363 rev. a | page 5 of 28 parameter b version 1 unit test conditions/comments digital outputs (sdo, busy , gpio, pec ) output low voltage 0.5 v max sinking 200 a output high voltage (sdo) dv cc ? 0.5 v min sourcing 200 a high impedance leakage current 5 a max sdo only high impedance output capacitance 2 10 pf typ temperature sensor (temp_out) 2 accuracy 1 c typ @ 25c 5 c typ ?40c < t < +85c output voltage at 25c 1.46 v typ output voltage scale factor 4.4 mv/c typ output load current 200 a max current source only power-on time 10 ms typ to within 5c power requirements dv cc 2.5/5.5 v min/v max v dd 8/16.5 v min/v max v ss ?16.5/?4.5 v min/v max power supply sensitivity 2 ?full scale/?v dd ?75 db typ ?full scale/?v ss ?75 db typ ?full scale/?dv cc ?90 db typ di cc 2 ma max dv cc = 5.5 v, v ih = dv cc , v il = gnd i dd 8.5 ma max outputs = 0 v and unloaded i ss 8.5 ma max outputs = 0 v and unloaded power-down mode bit 0 in the control register is 1 di cc 5 a typ i dd 35 a typ i ss ?35 a typ power dissipation power dissipation unloaded (p) 209 mw max v ss = ?12 v, v dd = 12 v, dv cc = 2.5 v junction temperature 4 130 c max t j = t a + p total ja 1 temperature range for b version: ?40c to +85c. typical specifications are at 25c. 2 guaranteed by design and characterization; not production tested. 3 voutx refers to any of vout0 to vout7. 4 ja represents the package thermal impedance.
ad5362/ad5363 rev. a | page 6 of 28 ac characteristics dv cc = 2.5 v; v dd = 15 v; v ss = ?15 v; v ref = 5 v; agnd = dgnd = siggnd0 = siggnd1 = 0 v; c l = 200 pf; r l = 10 k; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 3. parameter b version 1 unit test conditions/comments dynamic performance 1 output voltage settling time 20 s typ full-scale change 30 s max dac latch contents alternately loaded with all 0s and all 1s slew rate 1 v/s typ digital-to-analog glitch energy 5 nv-s typ glitch impulse peak amplitude 10 mv max channel-to-channel isolation 100 db typ vref0, vref1 = 2 v p-p, 1 khz dac-to-dac crosstalk 10 nv-s typ digital crosstalk 0.2 nv-s typ digital feedthrough 0.02 nv-s typ effect of input bus activity on dac output under test output noise spectral density @ 10 khz 250 nv/hz typ vref0 = vref1 = 0 v 1 guaranteed by design and characterization ; not production tested.
ad5362/ad5363 rev. a | page 7 of 28 timing characteristics dv cc = 2.5 v to 5.5 v; v dd = 9 v to 16.5 v; v ss = ?16.5 v to ?8 v; v ref = 5 v; agnd = dgnd = siggnd = 0 v; c l = 200 pf to gnd; r l = open circuit; gain (m), offset (c), and dac offset registers at default values; all specifications t min to t max , unless otherwise noted. table 4. spi interface parameter 1 , 2 , 3 limit at t min , t max unit description t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 11 ns min sync falling edge to sclk falling edge setup time t 5 20 ns min minimum sync high time t 6 10 ns min 24 th sclk falling edge to sync rising edge t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 4 42 ns max sync rising edge to busy falling edge t 10 1/1.5 s typ/s max busy pulse width low (single-channel update); see table 9 t 11 600 ns max single-channel update cycle time t 12 20 ns min sync rising edge to ldac falling edge t 13 10 ns min ldac pulse width low t 14 3 s max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 3 s max ldac falling edge to dac output response time t 17 20/30 s typ/s max da c output settling time t 18 140 ns max clr / reset pulse activation time t 19 30 ns min reset pulse width low t 20 400 s max reset time indicated by busy low t 21 270 ns min minimum sync high time in readback mode t 22 5 25 ns max sclk rising edge to sdo valid t 23 80 ns max reset rising edge to busy falling edge 1 guaranteed by design and characterization ; not production tested. 2 all input signals are specified with t r = t f = 2 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 4 and figure 5. 4 t 9 is measured with the load circuit shown in figure 2 . 5 t 22 is measured with the load circuit shown in figure 3 . to output pin c l 50pf r l 2.2k ? v ol dv cc 05762-002 v oh (min) ? v ol (max) 2 200a i ol 200a i oh t o output pin c l 50pf 0 5762-003 figure 2. load circuit for busy timing diagram figure 3. load circuit for sdo timing diagram
ad5362/ad5363 rev. a | page 8 of 2 8 sclk sync sdi busy v outx 1 v outx 2 voutx reset voutx clr 1 2 24 t 8 t 12 t 10 t 13 t 17 t 14 t 15 t 13 t 17 t 9 t 7 t 5 t 4 t 2 t 6 db23 db0 t 16 1 ldac active during busy. 2 ldac active after busy. busy ldac 1 ldac 2 1 t 3 t 20 t 23 t 18 t 18 t 19 24 t 11 t 1 05762-004 figure 4. spi write timing
ad5362/ad5363 rev. a | page 9 of 28 sdi sdo 48 nop condition selected register data clocked out t 22 t 21 lsb from previous write sclk sync db0 db0 db0 db0 db23 db23 db23 db15 input word specifies register to be read 05762-005 figure 5. spi read timing dac code full-scale error + zero-scale error zero-scale error v min 0 2 n ? 1 v max ideal transfer function n = 16 for ad5362 n = 14 for ad5363 actual transfer function output voltage 05762-006 figure 6. dac tr ansfer function
ad5362/ad5363 rev. a | page 10 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 60 ma do not cause scr latch-up. table 5. parameter rating v dd to agnd ?0.3 v to +17 v v ss to agnd ?17 v to +0.3 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv cc + 0.3 v digital outputs to dgnd ?0.3 v to dv cc + 0.3 v vref0, vref1 to agnd ?0.3 v to +5.5 v vout0 through vout7 to agnd v ss ? 0.3 v to v dd + 0.3 v siggnd0, siggnd1 to agnd ?1 v to +1 v agnd to dgnd ?0.3 v to +0.3 v mon_in0, mon_in1, mon_out to agnd v ss ? 0.3 v to v dd + 0.3 v operating temperature range (t a ) industrial (j version) ?40c to +85c storage temperature range ?65c to +150c operating junction temperature (t j max) 130c ja thermal impedance 52-lead lqfp 38c/w 56-lead lfcsp 25c/w reflow soldering peak temperature 230c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5362/ad5363 rev. a | page 11 of 28 pin configuration and fu nction descriptions 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 39 38 37 36 35 34 33 32 31 30 29 28 27 nc vout4 vout5 vout6 vout7 s iggnd1 nc nc nc nc nc nc nc ldac clr reset bin/2scomp busy gpio mon_out mon_in0 nc nc v dd v ss vref1 nc siggnd0 vout3 vout2 vout1 vout0 temp_out mon_in1 vref0 nc v ss v dd nc nc = no connect agnd dv cc sdo pec sdi sclk sync dv cc dgnd nc nc nc dgnd pin 1 indicator ad5362/ ad5363 top view (not to scale) 0 5762-007 pin 1 indicator ad5362/ ad5363 top view (not to scale) 05762-025 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 42 41 40 39 38 37 36 35 34 33 32 31 30 29 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 reset bin/2scomp busy gpio mon_out mon_in0 nc nc nc nc nc v dd v ss vref1 nc = no connect v o u t 4 v o u t 5 v o u t 6 v o u t 7 s i g g n d 1 n c n c n c n c n c n c n c n c n c nc nc nc nc siggnd0 vout3 vout2 vout1 vout0 temp_out mon_in1 vref0 nc nc v ss v dd c l r l d a c a g n d d g n d d v c c s d o p e c s d i s c l k s y n c d v c c d g n d figure 7. 52-lead lqfp pin configuration figure 8. 56-lead lfcsp pin configuration table 6. pin function descriptions pin no. mnemonic description lqfp lfcsp 1 55 ldac load dac logic input (active low). see the busy and ldac functions section for more information. 2 56 clr asynchronous clear input (level sensitive, active low). see the clear function section for more information. 3 1 reset digital reset input. 4 2 bin /2scomp data format digital input. connecting this pin to dgnd selects offset binary. setting this pin to 1 selects twos complement. this input has a weak pull-down. 5 3 busy digital input/open-drain output. busy is open drain when it is an output. see the busy and ldac functions section for more information. 6 4 gpio digital i/o pin. this pin can be configur ed as an input or output that can be read back or programmed high or low via the serial interface. when configured as an input, this pin has a weak pull-down. 7 5 mon_out analog multiplexer output. any dac output, the mon_in0 input, or the mon_in1 input can be routed to this output for monitoring. 8, 32 6, 34 mon_in0, mon_in1 analog multiplexer inputs. can be routed to mon_out. 9, 10, 14, 20 to 27, 30, 39 to 42 7 to 11, 15, 16, 22 to 28, 31, 32, 41 to 44 nc no connect. 11, 28 12, 29 v dd positive analog power supply; 9 v to 16.5 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 12, 29 13, 30 v ss negative analog power supply; ?16.5 v to ?8 v for specified performance. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 13 14 vref1 reference input for dac 4 to dac 7. this reference voltage is referred to agnd. 34 to 37, 15 to 18 36 to 39, 17 to 20 vout0 to vout7 dac outputs. buffered analog outputs for each of the eight dac channels. each analog output is capa ble of driving an output load of 10 k to ground. typical output impedance of these amplifiers is 0.5 . 19 21 siggnd1 reference ground for dac 4 to dac 7. vout4 to vout7 are referenced to this voltage. 31 33 vref0 reference input for dac 0 to dac 3. this reference voltage is referred to agnd.
ad5362/ad5363 rev. a | page 12 of 28 pin no. mnemonic description lqfp lfcsp 33 35 temp_out provides an output voltage proportional to the chip temperature, typically 1.46 v at 25c with an output variation of 4.4 mv/c. 38 40 siggnd0 reference ground for dac 0 to dac 3. vout0 to vout3 are referenced to this voltage. 43, 51 45, 53 dgnd ground for all digital circuitry. both dgnd pins should be connected to the dgnd plane. 44, 50 46, 52 dv cc logic power supply; 2.5 v to 5.5 v. these pins should be decoupled with 0.1 f ceramic capacitors and 10 f capacitors. 45 47 sync active low or sync input for spi interface. this is the frame synchronization signal for the spi serial interface. see , , and the section for more details. figure 4 figure 5 serial interface 46 48 sclk serial clock input for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 47 49 sdi serial data input for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 48 50 pec packet error check output. this is an open-drain output with a 50 k pull-up that goes low if the packet error check fails. 49 51 sdo serial data output for spi interface. see figure 4 , figure 5 , and the serial interface section for more details. 52 54 agnd ground for all analog circuitry. the agnd pin should be connected to the agnd plane. exposed paddle ep exposed paddle. connect to v ss .
ad5362/ad5363 rev. a | page 13 of 28 typical performance characteristics 0.0050 ?0.0050 05 time (s) amplitude (v) 0 0.0025 ?0.0025 1234 t a = 25c v ss = ?15v v dd = +15v v ref = +4.096v 05762-011 2 ?2 0 65535 dac code inl (lsb) 1 0 ?1 16384 32768 49152 05762-008 figure 12. digital crosstalk figure 9. typical ad5362 inl plot 1.0 ?1.0 08 temperature (c) inl error (lsb) 0 1.0 ?1.0 0 65535 dac code dnl (lsb) 0 0.5 ?0.5 16384 32768 49152 05762-012 0.5 0 ?0.5 20 40 60 v dd = +15v v ss = ?15v dv cc = +5v v ref = +3v 05762-009 figure 13. typical ad5362 dnl plot figure 10. typical inl error vs. temperature ?0.02 ?0.01 0 amplitude (v) 024681 time (s) 600 0 05 frequency (hz) output noise (nv/ hz) 200 300 400 500 100 123 4 05762-013 0 t a = 25c v ss = ?15v v dd = +15v v ref = +4.096v 0 5762-010 figure 11. analog crosstalk due to ldac figure 14. output noise spectral density
ad5362/ad5363 rev. a | page 14 of 28 0.50 0.45 0.40 0.35 0.30 0.25 ?40 80 temperature (c) di cc (ma) ?20 0 20 60 40 dv cc = +5.5v dv cc = +3.6v dv cc = +2.5v v ss = ?12v v dd = +12v v ref = +3v 05762-014 figure 15. di cc vs. temperature 6.5 6.0 5.5 5.0 4.5 ?40 80 temperature (c) i dd /i ss (ma) ?20 0 20 60 40 v ss = ?12v v dd = +12v v ref = +3v i ss i dd 05762-015 figure 16. i dd /i ss vs. temperature 14 12 10 8 6 4 2 0 5.8 6.0 6.2 6.4 6.6 v ss = ?15v v dd = +15v t a = 25c number of units i dd (ma) 05762-016 figure 17. typical i dd distribution 14 12 10 8 6 4 2 0 0.30 0.35 0.40 0.45 0.50 dv cc = 5v t a = 25c number of units di cc (ma) 0 5762-017 figure 18. typical di cc distribution 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ?40 ?25 ?10 5 20 35 50 65 80 voltage (v) temperature (c) 05762-018 figure 19. temp_out voltage vs. temperature mon_out current (ma) voutx ? mon_out (v) 1.0 ?1.0 ?1.0 ?1.0 0 0.5 ?0.5 ?0.5 0 0.5 full-scale zero-scale midscale 05762-019 figure 20. voutx mon_out error vs. mon_out current
ad5362/ad5363 rev. a | page 15 of 28 terminology integral nonlinearity (inl) integral nonlinearity, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (lsb). differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts, when the channel is at its mini- mum value. zero-scale error is mainly due to offsets in the output amplifier. full-scale error full-scale error is the error in the dac output voltage when all 1s are loaded into the dac register. full-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in millivolts, when the channel is at its maxi- mum value. full-scale error does not include zero-scale error. gain error gain error is the difference between full-scale error and zero-scale error. it is expressed as a percentage of the full- scale range (fsr). gain error = full-scale error ? zero-scale error vout temperature coefficient the vout temperature coefficient includes output error contributions from linearity, offset, and gain drift. dc output impedance dc output impedance is the effective output source resistance. it is dominated by package lead resistance. dc crosstalk the dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load current changes in one channel (due to an update), this change can result in a further dc change in one or more channel outputs. this effect is more significant at high load currents and is reduced as the load currents are reduced. with high impedance loads, the effect is virtually immeasurable. multiple v dd and v ss terminals are provided to minimize dc crosstalk. output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a full-scale input change. digital-to-analog glitch energy digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x7fff and 0x8000 (ad5362) or 0x1fff and 0x2000 (ad5363). channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dac reference input that appears at the output of another dac operating from another reference. it is expressed in decibels and measured at midscale. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter. it is specified in nv-s. digital crosstalk digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter. it is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the digital inputs of the device can be capacitively coupled both across and through the device to appear as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density output noise spectral density is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz.
ad5362/ad5363 rev. a | page 16 of 28 theory of operation dac architecture the ad5362/ad5363 contain eight dac channels and eight output amplifiers in a single package. the architecture of a single dac channel consists of a 16-bit (ad5362) or 14-bit (ad5363) resistor-string dac followed by an output buffer amplifier. the resistor-string section is simply a string of resistors, of equal value, from vref0 or vref1 to agnd. this type of architecture guarantees dac monotonicity. the 16-bit (ad5362) or 14-bit (ad5363) binary digital code loaded to the dac register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. the output amplifier multiplies the dac output voltage by 4. the nominal output span is 12 v with a 3 v reference and 20 v with a 5 v reference. channel groups the eight dac channels of the ad5362/ad5363 are arranged into two groups of four channels. the four dacs of group 0 derive their reference voltage from vref0. the four dacs of group 1 derive their reference voltage from vref1. each group has its own signal ground pin. table 7. ad5362/ad5363 registers register name word length in bits description x1a (group) (channel) 16 (14) input data register a, one for each dac channel. x1b (group) (channel) 16 (14) input data register b, one for each dac channel. m (group) (channel) 16 (14) gain trim registers, one for each dac channel. c (group) (channel) 16 (14) offset trim registers, one for each dac channel. x2a (group) (channel) 16 (14) output data register a, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. x2b (group) (channel) 16 (14) output data register b, one for each dac channel. these registers store the final, calibrated dac data after gain and offset trimming. they are not readable or directly writable. dac (group) (channel) data registers from which the dacs take their final input data. the dac registers are updated from the x2a or x2b registers. they are not readable or directly writable. ofs0 14 offset dac 0 data register: sets offset for group 0. ofs1 14 offset dac 1 data register: sets offset for group 1. control 5 bit 4 = overtemperature indicator. bit 3 = pec error flag. bit 2 = a /b select. bit 1 = thermal shutdown. bit 0 = software power-down. monitor 6 bit 5 = monitor enable. bit 4 = monitor dacs or monitor mon_inx pin. bit 3 to bit 0 = monitor selection control. gpio 2 bit 1 = gpio configuration. bit 0 = gpio data. a/b select 0 8 bits [3:0] in this register determine whether a dac in group 0 takes its data from register x2a or register x2b (0 = x2a, 1 = x2b). a/b select 1 8 bits [3:0] in this register determine whether a dac in group 1 takes its data from register x2a or register x2b (0 = x2a, 1 = x2b). table 8. ad5362/ad5363 input register default values register name ad5362 default value ad5363 default value x1a, x1b 0x8000 0x2000 m 0xffff 0x3fff c 0x8000 0x2000 ofs0, ofs1 0x2000 0x2000 control 0x00 0x00 a/b select 0 and a/b select 1 0x00 0x00
ad5362/ad5363 rev. a | page 17 of 28 a/b registers and gain/offset adjustment each dac channel has seven data registers. the actual dac data-word can be written to either the x1a or x1b input register, depending on the setting of the a /b bit in the control register. if the a /b bit is 0, data is written to the x1a register. if the a /b bit is 1, data is written to the x1b register. note that this single bit is a global control and affects every dac channel in the device. it is not possible to set up the device on a per- channel basis so that some writes are to x1a registers and some writes are to x1b registers. mux dac dac register mux x1a register x1b register m register c register x2a register x2b register 05762-020 figure 21. data registers associated with each dac channel each dac channel also has a gain (m) register and an offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain. data from the x1a register is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the x2a register. similarly, data from the x1b register is operated on by the multiplier and adder and stored in the x2b register. although a multiplier and an adder symbol are shown in figure 21 for each channel, there is only one multiplier and one adder in the device, which are shared among all channels. this has impli- cations for the update speed when several channels are updated at once, as described in the register update rates section. each time data is written to the x1a register, or to the m or c register with the a /b control bit set to 0, the x2a data is recal- culated and the x2a register is automatically updated. similarly, x2b is updated each time data is written to x1b, or to m or c with a /b set to 1. the x2a and x2b registers are not readable or directly writable by the user. data output from the x2a and x2b registers is routed to the final dac register by a multiplexer. a 4-bit a/b select register associated with each group of four dacs controls whether each individual dac takes its data from the x2a or x2b register. if a bit in this register is 0, the dac takes its data from the x2a register; if 1, the dac takes its data from the x2b register. note that because there are eight bits in two registers, it is possible to set up, on a per-channel basis, whether each dac takes its data from the x2a or x2b register. a global command is also provided that sets all bits in the a/b select registers to 0 or to 1. all dacs in the ad5362/ad5363 can be updated simultane- ously by taking ldac low when each dac register is updated from either its x2a or x2b register, depending on the setting of the a/b select registers. the dac register is not readable or directly writable by the user. ldac can be permanently tied low, and the dac output is updated whenever new data appears in the appropriate dac register. offset dacs in addition to the gain and offset trim for each dac, there are two 14-bit offset dacs, one for group 0 and one for group 1. these allow the output range of all dacs connected to them to be offset within a defined range. thus, subject to the limitations of headroom, it is possible to set the output range of group 0 or group 1 to be unipolar positive, unipolar negative, or bipolar, either symmetrical or asymmetrical about 0 v. the dacs in the ad5362/ad5363 are factory trimmed with the offset dacs set at their default values. this gives the best offset and gain perfor- mance for the default output range and span. when the output range is adjusted by changing the value of the offset dac, an extra offset is introduced due to the gain error of the offset dac. the amount of offset is dependent on the mag- nitude of the reference and how much the offset dac moves from its default value. see the specifications section for this offset. the worst-case offset occurs when the offset dac is at positive or negative full scale. this value can be added to the offset present in the main dac channel to give an indication of the overall offset for that channel. in most cases, the offset can be removed by programming the c register of the channel with an appropriate value. the extra offset caused by the offset dac needs to be taken into account only when the offset dac is changed from its default value. figure 22 shows the allowable code range that can be loaded to the offset dac, depending on the reference value used. thus, for a 5 v reference, the offset dac should not be programmed with a value greater than 8192 (0x2000). 0 4096 8192 12288 16383 offset dac code 0 1 2 3 4 v r e f ( v ) 5 reserved 0 5762-021 figure 22. offset dac code range
ad5362/ad5363 rev. a | page 18 of 28 output amplifier because the output amplifiers can swing to 1.4 v below the positive supply and 1.4 v above the negative supply, this limits how much the output can be offset for a given reference voltage. for example, it is not possible to have a unipolar output range of 20 v, because the maximum supply voltage is 16.5 v. clr clr clr dac channel offset dac output r6 10k ? r2 20k ? s3 s2 s1 r4 60k ? r3 20k ? siggndx siggndx r5 60k ? r1 20k ? 05762-022 figure 23. output ampl ifier and offset dac figure 23 shows details of a dac output amplifier and its connec- tions to the offset dac. on power-up, s1 is open, disconnecting the amplifier from the output. s3 is closed, so the output is pulled to siggndx (r1 and r2 are greater than r6). s2 is also closed to prevent the output amplifier from being open-loop. if clr is low at power-up, the output remains in this condition until clr is taken high. the dac registers can be programmed, and the outputs assume the programmed values when clr is taken high. even if clr is high at power-up, the output remains in this condition until v dd > 6 v and v ss < ?4 v and the initialization sequence has finished. the outputs then go to their power-on default value. transfer function the output voltage of a dac in the ad5362/ad5363 is depen- dent on the value in the input register, the value of the m and c registers, and the value in the offset dac. ad5362 transfer function the input code is the value in the x1a or x1b register that is applied to the dac (x1a, x1b default code = 32,768). dac_code = input_code ( m + 1)/2 16 + c ? 2 15 where: m = code in gain register ? default code = 2 16 C 1. c = code in offset register ? default code = 2 15 . the dac output voltage is calculated as follows: vout = 4 vref ( dac_code ? ( offset_code 4))/2 16 + v siggnd where: dac_code should be within the range of 0 to 65,535. for 12 v span, vref = 3.0 v. for 20 v span, vref = 5.0 v. offset_code is the code loaded to the offset dac. it is multiplied by 4 in the transfer function because this dac is a 14-bit device. on power-up, the default code loaded to the offset dac is 8192 (0x2000). with a 5 v reference, this gives a span of ?10 v to +10 v. ad5363 transfer function the input code is the value in the x1a or x1b register that is applied to the dac (x1a, x1b default code = 8192). dac_code = input_code ( m + 1)/2 14 + c ? 2 13 where: m = code in gain register ? default code = 2 14 C 1. c = code in offset register ? default code = 2 13 . the dac output voltage is calculated as follows: vout = 4 vref ( dac_code ? offset_code )/ 2 14 + v siggnd where: dac_code should be within the range of 0 to 16,383. for 12 v span, vref = 3.0 v. for 20 v span, vref = 5.0 v. offset_code is the code loaded to the offset dac. on power- up, the default code loaded to the offset dac is 8192 (0x2000). with a 5 v reference, this gives a span of ?10 v to +10 v. reference selection the ad5362/ad5363 have two reference input pins. the voltage applied to the reference pins determines the output voltage span on vout0 to vout7. vref0 determines the voltage span for vout0 to vout3 (group 0), and vref1 determines the voltage span for vout4 to vout7 (group 1). the reference voltage applied to each vref pin can be differ- ent, if required, allowing each group of four channels to have a different voltage span. the output voltage range and span can be adjusted further by programming the offset and gain registers for each channel as well as programming the offset dac. if the offset and gain features are not used (that is, the m and c registers are left at their default values), the required reference levels can be calculated as follows: vref = ( vout max ? vout min )/4 if the offset and gain features of the ad5362/ad5363 are used, the required output range is slightly different. the selected output range should take into account the system offset and gain errors that need to be trimmed out. therefore, the selected output range should be larger than the actual, required range. the required reference levels can be calculated as follows: 1. identify the nominal output range on vout. 2. identify the maximum offset span and the maximum gain required on the full output signal range. 3. calculate the new maximum output range on vout, including the expected maximum offset and gain errors. 4. choose the new required vout max and vout min , keep- ing the vout limits centered on the nominal values. note that v dd and v ss must provide sufficient headroom. 5. calculate the value of vref as follows: vref = ( vout max ? vout min )/4
ad5362/ad5363 rev. a | page 19 of 28 reference selection example if nominal output range = 20 v (?10 v to +10 v) offset error = 100 mv gain error = 3%, and siggnd = agnd = 0 v then gain error = 3% => maximum positive gain error = 3% => output range including gain error = 20 + 0.03(20) = 20.6 v offset error = 100 mv => maximum offset error span = 2(100 mv) = 0.2 v => output range including gain error and offset error = 20.6 v + 0.2 v = 20.8 v vref calculation actual output range = 20.6 v, that is, ?10.3 v to +10.3 v (centered); vref = (10.3 v + 10.3 v)/4 = 5.15 v if the solution yields an inconvenient reference level, the user can adopt one of the following approaches: ? use a resistor divider to divide down a convenient, higher reference level to the required level. ? select a convenient reference level above vref and modify the gain and offset registers to digitally downsize the reference. in this way, the user can use almost any convenient reference level but can reduce the performance by overcompaction of the transfer function. ? use a combination of these two approaches. calibration the user can perform a system calibration on the ad5362/ ad5363 to reduce gain and offset errors to below 1 lsb. this reduction is achieved by calculating new values for the m and c registers and reprogramming them. the m and c registers should not be programmed until both the zero-scale and full-scale errors are calculated. reducing zero-scale error zero-scale error can be reduced as follows: 1. set the output to the lowest possible value. 2. measure the actual output voltage and compare it to the required value. this gives the zero-scale error. 3. calculate the number of lsbs equivalent to the error and add this number to the default value of the c register. note that only negative zero-scale error can be reduced. reducing full-scale error full-scale error can be reduced as follows: 1. measure the zero-scale error. 2. set the output to the highest possible value. 3. measure the actual output voltage and compare it to the required value. add this error to the zero-scale error. this is the span error, which includes the full-scale error. 4. calculate the number of lsbs equivalent to the span error and subtract this number from the default value of the m register. note that only positive full-scale error can be reduced. ad5362 calibration example this example assumes that a ?10 v to +10 v output is required. the dac output is set to ?10 v but measured at ?10.03 v. this gives a zero-scale error of ?30 mv. 1 lsb = 20 v/65,536 = 305.176 v 30 mv = 98 lsbs the full-scale error can now be calculated. the output is set to 10 v and a value of 10.02 v is measured. this gives a full-scale error of +20 mv and a span error of +20 mv C (C30 mv) = +50 mv. 50 mv = 164 lsbs the errors can now be removed as follows: 1. add 98 lsbs to the default c register value: (32,768 + 98) = 32,866 2. subtract 164 lsbs from the default m register value: (65,535 ? 164) = 65,371 3. program the m register to 65,371; program the c register to 32,866. additional calibration the techniques described in the previous section are usually enough to reduce the zero-scale and full-scale errors in most applications. however, there are limitations whereby the errors may not be sufficiently reduced. for example, the offset (c) register can only be used to reduce the offset caused by the negative zero-scale error. a positive offset cannot be reduced. likewise, if the maximum voltage is below the ideal value, that is, a negative full-scale error, the gain (m) register cannot be used to increase the gain to compensate for the error. these limitations can be overcome by increasing the reference value. with a 2.5 v reference, a 10 v span is achieved. the ideal voltage range, for the ad5362 or the ad5363, is ?5 v to +5 v. using a +2.6 v reference increases the range to ?5.2 v to +5.2 v. clearly, in this case, the offset and gain errors are insignificant, and the m and c registers can be used to raise the negative voltage to ?5 v and then reduce the maximum voltage to +5 v to give the most accurate values possible.
ad5362/ad5363 rev. a | page 20 of 2 8 reset function the reset function is initiated by the reset pin. on the rising edge of reset , the ad5362/ad5363 state machine initiates a reset sequence to reset the x, m, and c registers to their default values. this sequence typically takes 300 s, and the user should not write to the part during this time. on power-up, it is recom- mended that the user bring reset high as soon as possible to properly initialize the registers. when the reset sequence is complete (and provided that clr is high), the dac output is at a potential specified by the default register settings, which is equivalent to siggndx. the dac outputs remain at siggndx until the x, m, or c register is updated and ldac is taken low. the ad5362/ad5363 can be returned to the default state by pulsing reset low for at least 30 ns. note that, because the reset function is triggered by the rising edge, bringing reset low has no effect on the operation of the ad5362/ad5363. clear function clr is an active low input that should be high for normal operation. the clr pin has an internal 500 k pull-down resistor. when clr is low, the input to each of the dac output buffer stages (vout0 to vout7) is switched to the externally set potential on the relevant siggndx pin. while clr is low, all ldac pulses are ignored. when clr is taken high again, the dac outputs return to their previous values. the contents of the input registers and dac register 0 to dac register 7 are not affected by taking clr low. to prevent glitches appearing on the outputs, clr should be brought low whenever the output span is adjusted by writing to the offset dac. busy and ldac functions the value of an x2 (a or b) register is calculated each time the user writes new data to the corresponding x1, c, or m registers. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c registers (see the section for more details), but no dac output updates can take place. register update rates the busy pin is bidirectional and has a 50 k internal pull-up resistor. when multiple ad5362 or ad5363 devices are used in one system, the busy pins can be tied together. this is useful when it is required that no da c in any device be updated until all other dacs are ready. when each device has finished updat- ing the x2 (a or b) registers, it releases the busy pin. if another device has not finished updating its x2 registers, it holds busy low, thus delaying the effect of ldac going low. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs are updated immediately after busy goes high. a user can also hold the ldac input permanently low. in this case, the dac outputs update immediately after busy goes high. whenever the a/b select registers are written to, busy also goes low, for approximately 600 ns. the ad5362/ad5363 have flexible addressing that allows writing of data to a single channel, all channels in a group, or all channels in the device. this means that one, two, four, or eight dac register values may need to be calculated and updated. because there is only one multiplier shared between eight channels, this task must be done sequentially, so the length of the busy pulse varies according to the number of channels being updated. table 9. busy pulse widths action busy pulse width 1 loading input, c, or m to 1 channel 2 1.5 s maximum loading input, c, or m to 2 channels 2.1 s maximum loading input, c, or m to 8 channels 5.7 s maximum 1 busy pulse width = ((number of cha nnels + 1) 600 ns) + 300 ns. 2 a single channel update is typically 1 s. the ad5362/ad5363 contain an extra feature whereby a dac register is not updated unless its x2a or x2b register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2a or x2b registers, depending on the setting of the a/b select registers. however, the ad5362/ ad5363 update the dac register only if the x2a or x2b data has changed, thereby removing unnecessary digital crosstalk. bin /2scomp pin the bin /2scomp pin determines if the output data is presented as offset binary or twos complement. if this pin is low, the data is straight binary. if it is high, the data is twos complement. this affects only the x, c, and offset dac registers; the m register and the control and command data are interpreted as straight binary. temperature sensor the on-chip temperature sensor provides a voltage output at the temp_out pin that is linearly proportional to the centigrade temperature scale. the typical accuracy of the temperature sensor is +1c at +25c and 5c over the ?40c to +85c range. its nominal output voltage is 1.46 v at 25c, varying at 4.4 mv/c. its low output impedance, low self- heating, and linear output simplify interfacing to temperature control circuitry and analog-to-digital converters.
ad5362/ad5363 rev. a | page 21 of 28 monitor function the ad5362/ad5363 contain a channel monitor function that consists of an analog multiplexer addressed via the serial interface, allowing any channel output to be routed to the mon_out pin for monitoring using an external adc. in addition, two monitor inputs, mon_in0 and mon_in1, are provided, which can also be routed to mon_out. the monitor function is controlled by the monitor register, which allows the monitor output to be enabled or disabled, and selects a dac channel or one of the monitor pins. when disabled, the monitor output is high impedance so that several monitor outputs can be connected in parallel with only one enabled at a time. table 10 shows the monitor register settings. table 10. monitor register functions f5 f4 f3 f2 f1 f0 function 0 x x x x x mon_out disabled 1 x x x x x mon_out enabled 1 0 0 0 0 0 mon_out = vout0 1 0 0 0 0 1 mon_out = vout1 1 0 0 0 1 0 mon_out = vout2 1 0 0 0 1 1 mon_out = vout3 1 0 1 0 0 0 mon_out = vout4 1 0 1 0 0 1 mon_out = vout5 1 0 1 0 1 0 mon_out = vout6 1 0 1 0 1 1 mon_out = vout7 1 1 0 0 0 0 mon_out = mon_in0 1 1 0 0 0 1 mon_out = mon_in1 the multiplexer is implemented as a series of analog switches. because this could conceivably cause a large amount of current to flow from the input of the multiplexer (voutx or mon_inx) to the output of the multiplexer (mon_out), care should be taken to ensure that whatever is connected to the mon_out pin is of high enough impedance to prevent the continuous current limit specification from being exceeded. because the mon_out pin is not buffered, the amount of current drawn from this pin creates a voltage drop across the switches, which in turn leads to an error in the voltage being monitored. where accuracy is important, it is recommended that the mon_out pin be buffered. figure 20 shows the typical error due to mon_out current. gpio pin the ad5362/ad5363 have a general-purpose i/o pin, gpio. this pin can be configured as an input or an output and read back or programmed (when configured as an output) via the serial interface. typical applications for this pin include moni- toring the status of a logic signal, a limit switch, or controlling an external multiplexer. the gpio pin is configured by writing to the gpio register, which has the special function code of 001101 (see table 15 and table 16 ). when bit f1 is set, the gpio pin becomes an output and bit f0 determines whether the pin is high or low. the gpio pin can be set as an input by writing 0 to both bit f1 and bit f0. the status of the gpio pin can be determined by initiating a read operation using the appropriate bits in table 17 . the status of the pin is indicated by the lsb of the register read. power-down mode the ad5362/ad5363 can be powered down by setting bit 0 in the control register to 1. this turns off the dacs, thus reducing the current consumption. the dac outputs are connected to their respective siggndx potentials. the power-down mode does not change the contents of the registers, and the dacs return to their previous voltage when the power-down bit is cleared to 0. thermal shutdown function the ad5362/ad5363 can be programmed to shut down the dacs if the temperature on the die exceeds 130c. setting bit 1 in the control register to 1 enables this function (see table 16 ). if the die temperature exceeds 130c, the ad5362/ad5363 enter a thermal shutdown mode, which is equivalent to setting the power-down bit in the control register. to indicate that the ad5362/ad5363 have entered thermal shutdown mode, bit 4 of the control register is set to 1. the ad5362/ad5363 remain in thermal shutdown mode, even if the die temperature falls, until bit 1 in the control register is cleared to 0. toggle mode the ad5362/ad5363 have two x2 registers per channel, x2a and x2b, which can be used to switch the dac output between two levels with ease. this approach greatly reduces the overhead required by a microprocessor, which would otherwise need to write to each channel individually. when the user writes to the x1a, x1b, m, or c register, the calculation engine takes a certain amount of time to calculate the appropriate x2a or x2b value. if an application, such as a data generator, requires that the dac output switch between two levels only, any method that reduces the amount of calculation time necessary is advantageous. for the data generator example, the user needs only to set the high and low levels for each channel once by writing to the x1a and x1b registers. the values of x2a and x2b are calculated and stored in their respective registers. the calculation delay, therefore, happens only during the setup phase, that is, when programming the initial values. to toggle a dac output between the two levels, it is only required to write to the relevant a/b select register to set the mux2 register bit. furthermore, because there are four mux2 control bits per register, it is possible to update eight channels with just two writes. table 18 shows the bits that correspond to each dac output.
ad5362/ad5363 rev. a | page 22 of 28 serial interface the ad5362/ad5363 contain a high speed spi operating at clock frequencies up to 50 mhz (20 mhz for read operations). to minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device is being written to, that is, on the falling edge of sync . the serial interface is 2.5 v lvttl-compatible when operating from a 2.5 v to 3.6 v dv cc supply. it is controlled by four pins: sync (frame synchronization input), sdi (serial data input pin), sclk (clocks data in and out of the device), and sdo (serial data output pin for data readback). spi write mode the ad5362/ad5363 allow writing of data via the serial inter- face to every register directly accessible to the serial interface, that is, all registers except the x2a, x2b, and dac registers. the x2a and x2b registers are updated when writing to the x1a, x1b, m, and c registers, and the dac data registers are updated by ldac . the serial word (see or ) is 24 bits long: 16 (ad5362) or 14 (ad5363) of these bits are data bits; six bits are address bits; and two bits are mode bits that determine what is done with the data. two bits are reserved on the ad5363. table 11 table 12 the serial interface works with both a continuous and a burst (gated) serial clock. serial data applied to sdi is clocked into the ad5362/ad5363 by clock pulses applied to sclk. the first falling edge of sync starts the write cycle. at least 24 falling clock edges must be applied to sclk to clock in 24 bits of data before sync is taken high again. if sync is taken high before the 24th falling clock edge, the write operation is aborted. if a continuous clock is used, sync must be taken high before the 25th falling clock edge. this inhibits the clock within the ad5362/ ad5363. if more than 24 falling clock edges are applied before sync is taken high again, the input data becomes corrupted. if an externally gated clock of exactly 24 pulses is used, sync can be taken high any time after the 24th falling clock edge. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be taken low again. spi readback mode the ad5362/ad5363 allow data readback via the serial interface from every register directly accessible to the serial interface, that is, all registers except the x2a, x2b, and dac data registers. to read back a register, it is first necessary to tell the ad5362/ad5363 which register is to be read. this is achieved by writing a word whose first two bits are the special function code 00 to the device. the remaining bits then determine which register is to be read back. if a readback command is written to a special function register, data from the selected register is clocked out of the sdo pin during the next spi operation. the sdo pin is normally three- stated but becomes driven as soon as a read command is issued. the pin remains driven until the register data is clocked out. see figure 5 for the read timing diagram. note that due to the timing requirements of t 22 (25 ns), the maximum speed of the spi interface during a read operation should not exceed 20 mhz. register update rates the value of the x2a register or the x2b register is calculated each time the user writes new data to the corresponding x1, c, or m register. the calculation is performed by a three-stage process. the first two stages take approximately 600 ns each, and the third stage takes approximately 300 ns. when the write to an x1, c, or m register is complete, the calculation process begins. if the write operation involves the update of a single dac channel, the user is free to write to another register, provided that the write operation does not finish until the first-stage calculation is complete, that is, 600 ns after the completion of the first write operation. if a group of channels is being updated by a single write operation, the first-stage calculation is repeated for each channel, taking 600 ns per channel. in this case, the user should not complete the next write operation until this time has elapsed. table 11. ad5362 serial word bit assignment i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 m1 m0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 12. ad5363 serial word bit assignment i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 1 i0 1 m1 m0 a5 a4 a3 a2 a1 a0 d13 d12 d11 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 bit i1 and bit i0 are reserved for future use and should be 0 when writing the serial word. these bits read back as 0.
ad5362/ad5363 rev. a | page 23 of 28 packet error checking to verify that data has been received correctly in noisy environ- ments, the ad5362/ad5363 offer the option of error checking based on an 8-bit (crc-8) cyclic redundancy check. the device controlling the ad5362/ad5363 should generate an 8-bit checksum using the polynomial c( x ) = x 8 + x 2 + x 1 + 1. this is added to the end of the data-word, and 32 data bits are sent to the ad5362/ad5363 before taking sync high. if the ad5362/ ad5363 see a 32-bit data frame, an error check is performed when sync goes high. if the checksum is valid, the data is written to the selected register. if the checksum is invalid, the packet error check ( pec ) output goes low and bit 3 of the control register is set. after reading the control register, bit 3 is cleared automatically and pec goes high again. sync sclk sdi 24-bit data transfer?no error checking sync sclk sdi msb d23 lsb d0 msb d31 lsb d8 d7 d0 update on sync high update after sync high only if error check passed 24-bit data 24-bit data 24-bit data transfer with error checking 8-bit fcs pec pec goes low if error check fails 05762-026 figure 24. spi write with and without error checking channel addressing and special modes if the mode bits are not 00, the data-word d15 to d0 (ad5362) or d13 to d0 (ad5363) is written to the device. address bit a4 to address bit a0 determine which channels are written to, and the mode bits determine to which register (x1a, x1b, c, or m) the data is written, as shown in table 13 and table 14 . data is to be written to the x1a register when the a /b bit in the control register is 0, or to the x1b register when the a /b bit is 1. the ad5362/ad5363 have very flexible addressing that allows the writing of data to a single channel, all channels in a group, or all channels in the device. table 14 shows which groups and which channels are addressed for every combination of address bit a4 to address bit a0. table 13. mode bits m1 m0 action 1 1 write to dac data (x) register 1 0 write to dac offset (c) register 0 1 write to dac gain (m) register 0 0 special function, used in combination with other bits of the data-word table 14. group and channel addressing address bit a2 to address bit a0 address bit a4 to address bit a3 00 01 10 11 000 all groups, all channels group 0, ch annel 0 group 1, channel 0 unused 001 group 0, all channels group 0, ch annel 1 group 1, channel 1 unused 010 group 1, all channels group 0, ch annel 2 group 1, channel 2 unused 011 unused group 0, channel 3 group 1, channel 3 unused 100 unused unused unused unused 101 unused unused unused unused 110 unused unused unused unused 111 unused unused unused unused
ad5362/ad5363 rev. a | page 24 of 28 special function mode if the mode bits are 00, the special function mode is selected, as shown in table 15 . bit i21 to bit i16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel addr ess for data readback. the codes for the special functions are shown in table 16 . table 17 shows the addresses for data readback. table 15. special function mode i23 i22 i21 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 0 0 s5 s4 s3 s2 s1 s0 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 table 16. special function codes special function code data (f15 to f0) action s5 s4 s3 s2 s1 s0 0 0 0 0 0 0 0000 0000 0000 0000 nop. 0 0 0 0 0 1 xxxx xxxx xxxx x [f2:f0] write control register. f4 = 1: temperature over 130c. f4 = 0: temperature below 130c. read-only bit. this bit should be 0 when writing to the control register. f3 = 1: pec error. f3 = 0: no pec error. reserved. read-only bit. this bit should be 0 when writing to the control register. f2 = 1: select register x1b for input. f2 = 0: select register x1a for input. f1 = 1: enable thermal shutdown mode. f1 = 0: disable thermal shutdown mode. f0 = 1: software power-down. f0 = 0: software power-up. 0 0 0 0 1 0 xx [f13:f0] write data in f13 to f0 to ofs0 register. 0 0 0 0 1 1 xx [f13:f0] write data in f13 to f0 to ofs1 register. 0 0 0 1 0 0 reserved 0 0 0 1 0 1 see table 17 select register for readback. 0 0 0 1 1 0 xxxx xxxx xxxx [f3:f0] write data in f3 to f0 to a/b select register 0. 0 0 0 1 1 1 xxxx xxxx xxxx [f3:f0] write data in f3 to f0 to a/b select register 1. 0 0 1 0 0 0 reserved 0 0 1 0 0 1 reserved 0 0 1 0 1 0 reserved 0 0 1 0 1 1 xxxx xxxx [f7:f0] block write to a/b select registers. f7 to f0 = 0: write all 0s (all channels use x2a register). f7 to f0 = 1: write all 1s (all channels use x2b register). 0 0 1 1 0 0 xxxx xxxx xx [f5:f0] f5 = 1: monitor enable. f5 = 0: monitor disable. f4 = 1: monitor input pin selected by f0. f4 = 0: monitor dac channel selected by f3:f0 (see table 10 ). f3 = not used if f4 = 1. f2 = not used if f4 = 1. f1 = not used if f4 = 1. f0 = 0: mon_in0 selected for monitoring (if f4 and f5 = 1). f0 = 1: mon_in1 selected for monitoring (if f4 and f5 = 1). 0 0 1 1 0 1 xxxx xxxx xxxx xx [f1:f0] gpio configure and write. f1 = 1: gpio is an outp ut. data to output is written to f0. f1 = 0: gpio is an input. data can be read from f0 on readback.
ad5362/ad5363 rev. a | page 25 of 28 table 17. address codes for data readback 1 f15 f14 f13 f12 f11 f10 f9 f8 f7 register read 0 0 0 x1a register 0 0 1 x1b register 0 1 0 c register 0 1 1 bit f12 to bit f7 select the channel to be read back; channel 0 = 001000 to channel 3 = 001011 channel 4 = 010000 to channel 7 = 010011 m register 1 0 0 0 0 0 0 0 1 control register 1 0 0 0 0 0 0 1 0 ofs0 data register 1 0 0 0 0 0 0 1 1 ofs1 data register 1 0 0 0 0 0 1 0 0 reserved 1 0 0 0 0 0 1 1 0 a/b select register 0 1 0 0 0 0 0 1 1 1 a/b select register 1 1 0 0 0 0 1 0 0 0 reserved 1 0 0 0 0 1 0 0 1 reserved 1 0 0 0 0 1 0 1 0 reserved 1 0 0 0 0 1 0 1 1 gpio read (data in f0) 2 1 bit f6 to bit f0 are dont cares for the data readback function. 2 bit f6 to bit f0 should be 0 for gpio read. table 18. dacs selected by a/b select registers bits 1 a/b select register f7 f6 f5 f4 f3 f2 f1 f0 0 reserved reserved reserved reserved dac 3 dac 2 dac 1 dac 0 1 reserved reserved reserved reserved dac 7 dac 6 dac 5 dac 4 1 if the bit is set to 0, register x2a is selected. if the bit is set to 1, register x2b is selected.
ad5362/ad5363 rev. a | page 26 of 28 applications information power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit boards on which the ad5362/ad5363 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5362/ad5363 are in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. for supplies with multiple pins (v ss , v dd , dv cc ), it is recommended that these pins be tied together and that each supply be decoupled only once. the ad5362/ad5363 should have ample supply decoupling of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi)typical of the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. digital lines running under the device should be avoided because they can couple noise onto the device. the analog ground plane should be allowed to run under the ad5362/ad5363 to avoid noise coupling. the power supply lines of the ad5362/ad5363 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. it is essential to minimize noise on the vref0 and vref1 lines. avoid crossover of digital and analog signals. traces on oppo- site sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best approach, but it is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. power supply sequencing when the supplies are connected to the ad5362/ad5363, it is important that the agnd and dgnd pins be connected to the relevant ground plane before the positive or negative supplies are applied. in most applications, this is not an issue because the ground pins for the power supplies are connected to the ground pins of the ad5362/ad5363 via ground planes. when the ad5362/ad5363 are to be used in a hot-swap card, care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are connected. this is required to prevent currents from flowing in directions other than toward an analog or digital ground. interfacing examples the spi interface of the ad5362/ad5363 is designed to allow the parts to be easily connected to industry-standard dsps and microcontrollers. figure 25 shows how the ad5362/ad5363 can connect to the analog devices, inc., blackfin? dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5362 or ad5363, and programmable i/o pins that can be used to set or read the state of the digital input or output pins associated with the interface. spiselx adsp-bf531 ad5362/ ad5363 sck mosi miso pf10 pf8 pf9 pf7 sync sclk sdi sdo reset clr ldac busy 05762-023 figure 25. interfacing to a blackfin dsp the analog devices adsp-21065l is a floating-point dsp with two serial ports (sports). figure 26 shows how one sport can be used to control the ad5362 or ad5363. in this example, the transmit frame synchronization (tfsx) pin is connected to the receive frame synchronization (rfsx) pin. similarly, the transmit and receive clocks (tclkx and rclkx) are also connected. the user can write to the ad5362/ad5363 by writing to the transmit register of the adsp-21065l. a read operation can be accom- plished by first writing to the ad5362/ad5363 to tell the part that a read operation is required. a second write operation with an nop instruction causes the data to be read from the ad5362/ad5363. the dsp receive interrupt can be used to indicate when the read operation is complete. sync sclk sdi sdo reset clr ldac busy ad5362/ ad5363 adsp-21065l tfsx rfsx tclkx rclkx dtxa drxa flag 0 flag 1 flag 2 flag 3 0 5762-024 figure 26. interfacing to an adsp-21065l dsp
ad5362/ad5363 rev. a | page 27 of 28 outline dimensions compliant to jedec standards ms-026-bcc top view (pins down) 40 52 1 14 13 26 27 39 0.65 bsc lead pitch 0.38 0.32 0.22 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.10 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 051706-a figure 27. 52-lead low profile quad flat package [lqfp] (st-52) dimensions shown in millimeters compliant to jedec standards mo-220-vlld-2 112805-0 pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.25 min exposed pad (bottom view) figure 28. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-1) dimensions shown in millimeters
ad5362/ad5363 rev. a | page 28 of 28 ordering guide model temperature range packag e description package option ad5362bstz 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 ad5362bstz-reel 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 AD5362BCPZ 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-1 AD5362BCPZ-reel7 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-1 eval-ad5362ebz 1 evaluation board ad5363bstz 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 ad5363bstz-reel 1 ?40c to +85c 52-lead low profile quad flat package [lqfp] st-52 ad5363bcpz 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-1 ad5363bcpz-reel7 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-1 eval-ad5363ebz 1 evaluation board 1 z = rohs compliant part. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05762-0- 3 /08(a)

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